Capacitance sensor with sensor capacitance compensation

ABSTRACT

A capacitance sensing circuit may include a switching circuit configured to generate a sensor current by charging and discharging a capacitive sensor electrode, and a current mirror that generates a mirror current based on the sensor current. Based on the mirror current, a measurement circuit generates an output signal representative of a capacitance of the capacitive sensor electrode.

RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.13/443,718, filed on Apr. 10, 2012, which is a Continuation of U.S.application Ser. No. 12/395,546, filed Feb. 27, 2009, now U.S. Pat. No.8,154,310, issue Apr. 10, 2012, which claims the benefit of priority tothe Provisional Patent Application Ser. No. 61/067,540, filed Feb. 27,2008, all of which are hereby incorporated by reference in theirentirety.

TECHNICAL FIELD

This disclosure relates to the field of user interface devices and, inparticular, to capacitive sensor devices.

BACKGROUND

Computing devices, such as notebook computers, personal data assistants(PDAs), kiosks, and mobile handsets, have user interface devices, whichare also known as human interface devices (HID). One user interfacedevice that has become more common is a touch-sensor pad (also commonlyreferred to as a touchpad). A basic notebook computer touch-sensor pademulates the function of a personal computer (PC) mouse. A touch-sensorpad is typically embedded into a PC notebook for built-in portability. Atouch-sensor pad replicates mouse X/Y movement by using two defined axeswhich contain a collection of sensor elements that detect the positionof a conductive object, such as a finger. Mouse right/left button clickscan be replicated by two mechanical buttons, located in the vicinity ofthe touchpad, or by tapping commands on the touch-sensor pad itself. Thetouch-sensor pad provides a user interface device for performing suchfunctions as positioning a pointer, or selecting an item on a display.These touch-sensor pads may include multi-dimensional sensor arrays fordetecting movement in multiple axes. The sensor array may include aone-dimensional sensor array, detecting movement in one axis. The sensorarray may also be two dimensional, detecting movements in two axes.

One type of touchpad operates by way of capacitance sensing utilizingcapacitance sensors. The capacitance, detected by a capacitance sensor,changes as a function of the proximity of a conductive object to thesensor. The conductive object can be, for example, a stylus or a user'sfinger. In a touch-sensor device, a change in capacitance detected byeach sensor in the X and Y dimensions of the sensor array due to theproximity or movement of a conductive object can be measured by avariety of methods. Regardless of the method, usually an electricalsignal representative of the capacitance detected by each capacitivesensor is processed by a processing device, which in turn produceselectrical or optical signals representative of the position of theconductive object in relation to the touch-sensor pad in the X and Ydimensions. A touch-sensor strip, slider, or button operates on the samecapacitance-sensing principle.

A first type of conventional touchpad is composed of a matrix of rowsand columns. Within each row or column, there are multiple sensorelements. However, all sensor pads within each row or column are coupledtogether and operate as one long sensor element. A second type ofconventional touchpad is composed of an XY array of independent senseelements, where each sensor element in a row or column is separatelysensed. Here, each row and column is composed of multiple sensingelements, each capable of independent detection of a capacitive presenceand magnitude. These may then be used to detect any number ofsubstantially simultaneous touches.

The capacitive sensing systems used in interface devices such astouchpads generally operate by detecting changes in the capacitances ofthe capacitive sensors resulting from proximity or contact of an objectwith the sensor, however the ability to resolve changes in capacitancemay be impaired if the changes in capacitance to be detected by thesensor are small relative to the capacitance of the sensor. Forinstance, a capacitive sensor element that is configured to detect aninput, such as proximity or contact with a finger or other object, mayhave a capacitance C_(P) between the sensor element and ground when noinput is present. The capacitance C_(P) is known as the parasiticcapacitance of the sensor. For capacitive sensors having multiple senseelements, a mutual capacitance C_(M) may also be present between two ormore sense elements. An input detected by the sensor may cause a changein capacitance C_(F) that is much smaller than C_(P) or C_(M).Accordingly, where the sensor capacitance is represented as a digitalcode, the parasitic or mutual capacitances may be represented by alarger proportion of the discrete capacitance levels resolvable by thedigital code, while the capacitance change C_(F) is represented by fewerof these discrete levels. In such cases, the capacitance change C_(F)due to an input may not be resolvable to a high degree of resolution.

Additionally, the design of some capacitive sensors also results in ahigh susceptibility to noise due to electromagnetic interference (EMI).For example, a capacitive touchpad or slider device may include an arrayof capacitive sensor elements, each of which may include a conductivetrace having a substantial length. Such conductive traces may couplenoise into a capacitance measurement circuit and reduce the ability ofthe measurement circuit to measure capacitance levels accurately andprecisely.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is illustrated by way of example, and not by wayof limitation, in the figures of the accompanying drawings.

FIG. 1 illustrates a block diagram of one embodiment of an electronicsystem in which a capacitance sensor is used;

FIG. 2 is a circuit diagram illustrating a circuit for measuringcapacitance of a capacitive sensor, according to one embodiment;

FIG. 3A is a block diagram illustrating a connection between acapacitive sensor and an integrated circuit chip, according to oneembodiment;

FIG. 3B is a circuit diagram illustrating equivalent impedances of acapacitance measurement circuit in an integrated circuit chip, accordingto one embodiment;

FIG. 4 is a circuit diagram illustrating one embodiment of a capacitancesensing circuit including a current mirror;

FIG. 5 illustrates one embodiment of a capacitance measurement circuitimplemented in an integrated circuit chip;

FIG. 6 illustrates one embodiment of a capacitance measuring circuitimplemented in an integrated circuit chip;

FIG. 7A is a graph illustrating signals associated with the operation ofa capacitance sensing circuit, according to one embodiment;

FIG. 7B is a graph illustrating signals associated with the operation ofa capacitive sensing circuit, according to one embodiment;

FIG. 8 is a flow diagram illustrating a process for sensing capacitanceof a capacitive sensor, according to one embodiment; and

FIG. 9 is a flow diagram illustrating a process using a mirror currentfor measuring the capacitance of a capacitive sensor, according to oneembodiment.

DETAILED DESCRIPTION

Described herein are embodiments of a method and apparatus for measuringa capacitance of a capacitive sensor while compensating for a baselinecapacitance of the sensor and maintaining a low input impedance forincreasing noise immunity. The following description sets forth numerousspecific details such as examples of specific systems, components,methods, and so forth, in order to provide a good understanding ofseveral embodiments of the present invention. It will be apparent to oneskilled in the art, however, that at least some embodiments of thepresent invention may be practiced without these specific details. Inother instances, well-known components or methods are not described indetail or are presented in simple block diagram format in order to avoidunnecessarily obscuring the present invention. Thus, the specificdetails set forth are merely exemplary. Particular implementations mayvary from these exemplary details and still be contemplated to be withinthe spirit and scope of the present invention.

Embodiments of a method and apparatus for measuring capacitance of acapacitive sensor are described. In one embodiment, a capacitancesensing circuit detects an input at the capacitive sensor by detecting achange in the capacitance of a sensor element. For example, a fingerplaced near the capacitive sensor may cause an increase C_(F) in thecapacitance of the sensor. The magnitude of C_(F) may be detected andconverted to a voltage level or a digital code (by a capacitance-to-codeconversion circuit) that can be processed by a computer or othercircuit.

One embodiment of a capacitive sensor includes a positive electrodeconnected to a voltage source and a negative electrode connected toground. The capacitance of such a capacitive sensor can be measured byrepeatedly charging the positive electrode of the sensor from a voltagesource and discharging the positive electrode to ground, causing asensor current to flow between the voltage source and ground. Since theflow of the sensor current depends on the capacitance of the sensor, thesensor current can be measured to determine the capacitance of thesensor.

A portion of the sensor current may be attributable to a baselinecapacitance C_(B), which represents a total capacitance of thecapacitive sensor when no input (i.e., a finger touch) is present. Thebaseline capacitance may include the mutual capacitance C_(M) betweenthe positive and the negative electrodes, and/or the parasiticcapacitance C_(P) between each of the electrodes and other conductors(e.g., printed circuit board (PCB) traces or electrodes of othercapacitive sensors).

The ability of a digital code to resolve many levels of C_(F) (whichrepresents a change in capacitance of the capacitive sensor resultingfrom an input such as a finger touch) may be degraded if the baselinecapacitance C_(B) is large in comparison to C_(F). Therefore, thedynamic range of a capacitance-to-code conversion circuit may not beused effectively, since C_(F) is measured in the presence of the largebase value of C_(B). Thus, in one embodiment, the effects of thebaseline capacitance C_(B) are compensated using a current source tocancel the portion of the sensor current attributable to the baselinecapacitance. This allows the digital code to resolve C_(F) using agreater number of discrete levels, increasing the dynamic rangeutilization of the capacitance sensing circuit.

In one embodiment, a current mirror generates a mirror current based onthe sensor current. A measurement circuit measures the mirror currentrather than measuring the sensor current directly. The presence of thecurrent mirror decreases the input impedance seen by the capacitivesensor. The decreased input impedance increases immunity of themeasurement circuit to low frequency noise that is coupled to the systemthrough the capacitive sensor or other conductors, such as PCB traces.Additionally, the current mirror isolates the measurement circuit fromthe voltage supply used to charge the capacitive sensor so that thevoltage supply is not limited by the input requirements of themeasurement circuit.

FIG. 1 illustrates a block diagram of one embodiment of an electronicsystem in which a capacitance sensor with baseline capacitancecompensation circuit and current mirror can be implemented. Electronicsystem 100 includes processing device 110, touch-sensor pad 120,touch-sensor slider 130, touch-sensor buttons 140, host processor 150,embedded controller 160, and non-capacitance sensor elements 170. Theprocessing device 110 may include analog and/or digital general purposeinput/output (“GPIO”) ports 107. GPIO ports 107 may be programmable.GPIO ports 107 may be coupled to a Programmable Interconnect and Logic(“PIL”), which acts as an interconnect between GPIO ports 107 and adigital block array of the processing device 110 (not illustrated). Thedigital block array may be configured to implement a variety of digitallogic circuits (e.g., DACs, digital filters, or digital control systems)using, in one embodiment, configurable user modules (“UMs”). The digitalblock array may be coupled to a system bus. Processing device 110 mayalso include memory, such as random access memory (RAM) 105 and programflash 104. RAM 105 may be static RAM (SRAM), and program flash 104 maybe a non-volatile storage, which may be used to store firmware (e.g.,control algorithms executable by processing core 102 to implementoperations described herein). Processing device 110 may also include amemory controller unit (MCU) 103 coupled to memory and the processingcore 102.

The processing device 110 may also include an analog block array (notillustrated). The analog block array is also coupled to the system bus.Analog block array also may be configured to implement a variety ofanalog circuits (e.g., ADCs or analog filters) using, in one embodiment,configurable UMs. The analog block array may also be coupled to the GPIO107.

As illustrated, capacitance sensing circuit 101 may be integrated intoprocessing device 110. Capacitance sensing circuit 101 may includeanalog I/O for coupling to an external component, such as touch-sensorpad 120, touch-sensor slider 130, touch-sensor buttons 140, and/or otherdevices. Capacitance sensing circuit 101 and processing device 102 aredescribed in more detail below.

The embodiments described herein are not limited to touch-sensor padsfor notebook implementations, but can be used in other capacitivesensing implementations, for example, the sensing device may be a touchscreen, a touch-sensor slider 130, or touch-sensor buttons 140 (e.g.,capacitance sensing buttons). In one embodiment, these sensing devicesmay include one or more capacitive sensors. It should also be noted thatthe embodiments described herein may be implemented in other sensingtechnologies than capacitive sensing, such as resistive, opticalimaging, surface wave, infrared, dispersive signal, and strain gaugetechnologies. Similarly, the operations described herein are not limitedto notebook pointer operations, but can include other operations, suchas lighting control (dimmer), volume control, graphic equalizer control,speed control, or other control operations requiring gradual or discreteadjustments. It should also be noted that these embodiments ofcapacitive sensing implementations may be used in conjunction withnon-capacitive sensing elements, including but not limited to pickbuttons, sliders (ex. display brightness and contrast), scroll-wheels,multi-media control (ex. volume, track advance, etc) handwritingrecognition and numeric keypad operation.

In one embodiment, the electronic system 100 includes a touch-sensor pad120 coupled to the processing device 110 via bus 121. Touch-sensor pad120 may include a multi-dimension sensor array. The multi-dimensionsensor array includes multiple sensor elements, organized as rows andcolumns. In another embodiment, the electronic system 100 includes atouch-sensor slider 130 coupled to the processing device 110 via bus131. Touch-sensor slider 130 may include a single-dimension sensorarray. The single-dimension sensor array includes multiple sensorelements, organized as rows, or alternatively, as columns. In anotherembodiment, the electronic system 100 includes touch-sensor buttons 140coupled to the processing device 110 via bus 141. Touch-sensor buttons140 may include a single-dimension or multi-dimension sensor array. Thesingle- or multi-dimension sensor array may include multiple sensorelements. For a touch-sensor button, the sensor elements may be coupledtogether to detect a presence of a conductive object over the entiresurface of the sensing device. Alternatively, the touch-sensor buttons140 may have a single sensor element to detect the presence of theconductive object. In one embodiment, touch-sensor buttons 140 mayinclude a capacitive sensor element. Capacitive sensor elements may beused as non-contact sensor elements. These sensor elements, whenprotected by an insulating layer, offer resistance to severeenvironments.

The electronic system 100 may include any combination of one or more ofthe touch-sensor pad 120, touch-sensor slider 130, and/or touch-sensorbutton 140. In another embodiment, the electronic system 100 may alsoinclude non-capacitance sensor elements 170 coupled to the processingdevice 110 via bus 171. The non-capacitance sensor elements 170 mayinclude buttons, light emitting diodes (LEDs), and other user interfacedevices, such as a mouse, a keyboard, or other functional keys that donot require capacitance sensing. In one embodiment, buses 171, 141, 131,and 121 may be a single bus. Alternatively, these buses may beconfigured into any combination of one or more separate buses.

Processing device 110 may include internal oscillator/clocks 106 andcommunication block 108. The oscillator/clocks block 106 provides clocksignals to one or more of the components of processing device 110.Communication block 108 may be used to communicate with an externalcomponent, such as a host processor 150, via host interface (I/F) line151. Alternatively, processing block 110 may also be coupled to embeddedcontroller 160 to communicate with the external components, such as host150. In one embodiment, the processing device 110 is configured tocommunicate with the embedded controller 160 or the host 150 to sendand/or receive data.

Processing device 110 may reside on a common carrier substrate such as,for example, an integrated circuit (IC) die substrate, a multi-chipmodule substrate, or the like. Alternatively, the components ofprocessing device 110 may be one or more separate integrated circuitsand/or discrete components. In one exemplary embodiment, processingdevice 110 may be a Programmable System on a Chip (PSoC™) processingdevice, manufactured by Cypress Semiconductor Corporation, San Jose,Calif. Alternatively, processing device 110 may be one or more otherprocessing devices known by those of ordinary skill in the art, such asa microprocessor or central processing unit, a controller,special-purpose processor, digital signal processor (DSP), anapplication specific integrated circuit (ASIC), a field programmablegate array (FPGA), or the like.

It should also be noted that the embodiments described herein are notlimited to having a configuration of a processing device coupled to ahost, but may include a system that measures the capacitance on thesensing device and sends the raw data to a host computer where it isanalyzed by an application. In effect the processing that is done byprocessing device 110 may also be done in the host.

Capacitance sensing circuit 101 may be integrated into the IC of theprocessing device 110, or alternatively, in a separate IC.Alternatively, descriptions of capacitance sensing circuit 101 may begenerated and compiled for incorporation into other integrated circuits.For example, behavioral level code describing capacitance sensingcircuit 101, or portions thereof, may be generated using a hardwaredescriptive language, such as VHDL or Verilog, and stored to amachine-accessible medium (e.g., CD-ROM, hard disk, floppy disk, etc.).Furthermore, the behavioral level code can be compiled into registertransfer level (“RTL”) code, a netlist, or even a circuit layout andstored to a machine-accessible medium. The behavioral level code, theRTL code, the netlist, and the circuit layout all represent variouslevels of abstraction to describe capacitance sensing circuit 101.

It should be noted that the components of electronic system 100 mayinclude all the components described above. Alternatively, electronicsystem 100 may include only some of the components described above.

In one embodiment, electronic system 100 may be used in a notebookcomputer. Alternatively, the electronic device may be used in otherapplications, such as a mobile handset, a personal data assistant (PDA),a keyboard, a television, a remote control, a monitor, a handheldmulti-media device, a handheld video player, a handheld gaming device,or a control panel.

FIG. 2 is a circuit diagram illustrating a circuit for measuringcapacitance of a capacitive sensor, according to one embodiment.Capacitance sensing circuit 200 may be included in an electronic system,such as electronic system 100.

Capacitive sensing circuit 200 includes capacitive sensor 221, switchingcircuit 220, compensation circuit 240, current mirror 260, andmeasurement circuit 280. Switching circuit 220 includes switches 223 and222, through which sensor current I_(S) 224 flows. Compensation circuit240 includes current digital-to-analog converter (IDAC) 241 that outputsa compensation current I_(C) 242 that flows into node 225. Currentmirror 260 includes transistors 264 and 265, which are connected throughresistors R₁ 262 and R₂ 263, respectively, to supply voltage V_(CC).Compensated sensor current I_(D) 261 flows out of transistor 264 andmirror current I_(M) flows out of transistor 265. Measurement circuit280 includes an integration capacitor C_(INT) connected to an input of acomparator 284, a timer 285 connected to the output of the comparator284, and an oscillator 286 connected to the timer 285. The output ofcomparator 284 is also connected to a discharge switch 281 thatdischarges C_(INT) 282.

In one embodiment, the capacitive sensor 221 is a sensor having acapacitance that is affected by the proximity of a conductive object,such as a finger. The capacitive sensor 221 is repeatedly charged anddischarged by switching circuit 220. In one embodiment, switches 222 and223 are operated in a non-overlapping manner (so that both switches arenot simultaneously closed) to charge and discharge capacitive sensor221. For example, switch 222 connects sensor 221 to a positive voltagesupply V_(CC), charging sensor 221. Switch 222 opens and switch 223closes, discharging sensor 221 to ground. The repeated charging anddischarging of the sensor 221 results in the flow of sensor currentI_(S) 224 from node 225 to ground. Thus, the combination of capacitivesensor 221 and switching circuit 220 can be represented as an equivalentresistance R_(S) that conducts sensor current I_(S) 224 between node 225and ground.

Compensation circuit 240 compensates for a baseline capacitance C_(B) ofthe capacitive sensor 221 by supplying a compensation current I_(C) 242to the capacitive sensor 221. Specifically, the compensation currentsupplies I_(C) 242 into node 225 connected to the sensor 221 throughswitch 222. In one embodiment, I_(C) 242 is approximately equal to theamount of current attributable to the baseline capacitance of sensor221. For example, I_(C) 242 may be chosen so that the net currentflowing into node 225 is zero when no input is present at capacitivesensor 221. In one embodiment, I_(C) 242 is supplied from a currentdigital-to-analog converter (IDAC) 241, which is programmed to output adesired compensation current I_(C) 242.

In addition to the switching circuit 220 and the compensation circuit240, node 225 is also connected to current mirror 260. Compensatedsensor current I_(D) 261, which is the difference between I_(C) 242 andI_(S) 224, flows from transistor 264 of current mirror 260 into node225. The magnitude of I_(D) 261 indicates the magnitude of a change incapacitance C_(F) at capacitive sensor 221. For example, when no inputis present at capacitive sensor 221, I_(S) 224 is equal to I_(C) 242 sothat I_(D) 261 is zero. When the capacitance at capacitive sensor 221 isincreased by an input at capacitive sensor 221, the amount of chargestored in sensor 221 and then discharged to ground increases with thecapacitance. Thus, the sensor current I_(S) 224 and the compensatedsensor current I_(D) 261 also increase.

The compensated sensor current I_(D) 261 flows out of the transistor 264and is mirrored by transistor 265 to generate a mirror current I_(M)266. In one embodiment, I_(M) 266 is approximately equal to I_(D). Inalternative embodiments, the current mirror 260 amplifies I_(D) so thatI_(M) is proportionally greater or less than I_(D) by a desiredamplification factor. For example, a high voltage may be used to chargesensor 221, resulting in a large value of I_(D) 261 that is outside theoperating range of measurement circuit 280. The current mirror 260 cangenerate a reduced mirror current I_(M) 266, corresponding to I_(D) 261,that is within the operating range of the measurement circuit 280.

The measurement circuit 280 receives the mirror current I_(M) 266 as aninput. I_(M) 266 is used to charge integration capacitor C_(INT) 282 sothat the voltage at C_(INT) increases over time. The voltage of C_(INT)is applied to an input of comparator 284. Comparator 284 compares thevoltage of C_(INT) with a reference voltage V_(RFF) 283. When theC_(INT) voltage exceeds V_(REF) 283, the comparator outputs a signal totimer 285. The output of comparator 284 is also connected to dischargeswitch 281 so that discharge switch 281 discharges C_(INT) when thevoltage of C_(INT) exceeds V_(REF) 283, preparing C_(INT) for the nextcharge cycle.

Comparator 284 thus outputs a series of pulses as the voltage of C_(INT)exceeds V_(REF) 283 and subsequently drops below V_(REF) 283 as C_(INT)is discharged. Timer 285 detects the time between these pulses andoutputs a count value that corresponds to the capacitance of sensor 221.For example, the duration between pulses output by the comparator 284decreases with an increase in the mirror current I_(M) 266 because ahigher I_(M) charges C_(INT) more quickly. In one embodiment, timer 285counts the number of oscillations from oscillator 286 between pulsesfrom the comparator 284.

FIG. 3A is a block diagram illustrating a connection between acapacitive sensor 221 and an integrated circuit chip 303, according toone embodiment. Capacitive sensor 221 is connected to input pin 302 ofintegrated circuit chip 303 through a printed circuit board (PCB) trace301. Within the integrated circuit chip 303, input pin 302 is connectedto a measurement circuit 280.

In one embodiment, the capacitive sensor 221 and PCB trace 301 areunshielded conductors and are susceptible to electromagneticinterference (EMI). Noise caused by EMI may be coupled into themeasurement circuit 280 through input pin 302, where it may cause errorin the measurement of capacitive sensor 221.

FIG. 3B is a circuit diagram illustrating equivalent impedances of acapacitance measurement circuit in an integrated circuit chip, accordingto one embodiment. In one embodiment, EMI immunity is inverselyproportional to the input impedance of the measurement circuit 280. Thisinput impedance can be modeled as a filter capacitance C_(FILT) 316 thatreduces the effect of radio frequency (RF) noise coupling at highfrequencies. In addition, the input impedance includes an inductivecomponent, modeled as a parasitic inductor L_(PAR) 315, and a seriesresistance R_(SER) 314. L_(PAR) 315 and R_(SER) 314 reduce the noisesuppression effect of C_(FILT) 316 at high frequencies. In oneembodiment, a smaller value of C_(FILT) 316 may be used to maintain ahigh sensor scanning speed, so that C_(FILT) 316 may not providereliable high frequency noise suppression.

The IDAC, such as IDAC 241, can be modeled as a resistance R_(IDAC) 317.R_(IDAC) 317 provides an additional low impedance to ground, parallel toC_(FILT) 316, L_(PAR) 315, and R_(SER) 314. The series resistanceR_(MUX) 313 represents the impedance of an analog multiplexer bus (whichwill be described later with reference to FIG. 5) through which thecapacitive sensor 221 is connected to the measurement circuit 280.

A measurement circuit 280 that includes a current mirror, such ascurrent mirror 260, also has a resistance R_(CM) 318 to model theimpedance of the current mirror. R_(CM) 318 provides an impedancebetween the input pin 312 and ground, and thus decreases the total inputimpedance of the measurement circuit 280.

For example, if the resistance of R_(MUX) 313 resistance is about 400□,the impedance of C_(FILT) 316 at 1 MHz is about 1.6 k□, and the IDACimpedance R_(IDAC) 317 is about 100 k□, then the input impedance of themeasurement circuit 280 without R_(CM) is about 1.6 k□ at 1 MHz.

When R_(CM) is included, the input impedance of the measurement circuit280 decreases. For example, a typical value for R_(CM) may be 300-4000□.In this case input impedance of the measurement circuit 280 at 1 MHz isabout 700□, which is three times lower than in a measurement circuit 280that does not include R_(CM). Thus, the decreased resistance to groundprovided by the current mirror increases immunity to low frequencynoise.

FIG. 4 is a circuit diagram illustrating an embodiment of a capacitancesensing circuit including a current mirror. Capacitance sensing circuit200 may be included in an electronic system, such as electronic system100.

Capacitive sensing circuit 400 includes capacitive sensor 421, switchingcircuit 420, and compensation circuit 440, current mirror 460. Switchingcircuit 220 includes switches 422 and 423, through which sensor currentI_(S) 424 flows from V_(DD) to node 425. Compensation circuit 440includes current digital-to-analog converter (IDAC) 441 that sinks acompensation current I_(C) 442 out of node 425. Current mirror 460includes transistors 464 and 465, which are connected through resistorsR₁ 462 and R₂ 463, respectively, to ground. Transistor 465 is connectedto V_(DD) through R₃ 467. Compensated sensor current I_(D) 461 flowsthrough R₃ 467 and into node 481. The output of comparator 484 isconnected to a discharge switch 481 that discharges C_(INT) 282.

Capacitive sensor 421 and switching circuit 420 operate in similarfashion as capacitive sensor 221 and switching circuit 220 as describedwith reference to FIG. 2, except that the operation of switching circuit420 causes a sensor current I_(S) 424 to flow from a voltage source VDDinto node 425. Specifically, switches 422 and 423 operate in anon-overlapping manner to alternately connected capacitive sensor 421 toVDD and then to node 425. Thus, the sensor 421 is charged from VDD anddischarged into node 425, resulting in the flow of I_(S) 424 into node425. In one embodiment, the sensor current I_(S) 424 into node 425increases when a conductive object is placed near capacitive sensor 421.

Compensation circuit 440 includes an IDAC 441 that is connected to node425. Similar to the IDAC 241 of compensation circuit 220 in FIG. 2, theIDAC 441 can be used to compensate for a baseline capacitance C_(B) ofcapacitive sensor 421. IDAC 441 draws a compensation current I_(C) 442out of node 425. In one embodiment, I_(C) 442 is approximately equal toI_(S) 424 when no input is present at capacitive sensor 421.

The current out of node 425 represents the difference between the sensorcurrent I_(S) 424 and the compensation current I_(C) 442. I_(D) 461flows to ground through transistor 464 and resistor R₁ 462. Currentmirror 460 generates a mirror current I_(M) 466 through transistor 465based on the current I_(D) 461 flowing through transistor 464. In oneembodiment, I_(M) 466 is approximately equal to I_(D) 461. In analternative embodiment, the current mirror 460 amplifies I_(D) 461 sothat I_(M) 466 is proportional to I_(D) 461.

I_(M) 466 flows through R₃ 467 such that the sense voltage 482 at node481 is V_(DD)−I_(M)×R₃. Thus, since the mirror current I_(M) 466corresponds to the capacitance of capacitive sensor 421, the sensevoltage can be measured to determine the capacitance of the sensor 421.

FIG. 5 illustrates one embodiment of a capacitance measurement circuitimplemented in an integrated circuit chip. Integrated circuit chip 500includes a system clock 510 connected to switches 522 and 523, an analogmultiplexer bus 530 with a capacitance C₁ 531 to ground, a currentdigital-to-analog converter (MAC) 541, and a general purposeinput/output (GPIO) port 520. Integrated circuit chip 500 interfaceswith external components through input pins 502 and 504, and output pin503.

Capacitive sensor 521 connects to switches 522 and 523 through input pin502. Current mirror 560 is connected to analog multiplexor bus throughoutput pin 503. Current mirror 560 is also connected to supply voltageV_(CC) through resistors R₁ 562 and R₂ 563. A mirror current I_(M) 566flows from the current mirror 560 to ground through resistor R₃ 567.GPIO port 520 is connected to R₃ 567 to monitor the voltage across R₃567.

The switches 522 and 523 are controlled by the system clock 510 so thatthey operate in similar fashion as switches 222 and 223 of capacitancesensing circuit 200 illustrated in FIG. 2. Switches 522 and 523 thuscharge and discharge the sensor 521 to cause a sensor current I_(S) toflow into the analog multiplexer bus 530.

IDAC 541 supplies a compensation current to the bus 530 to compensatefor a portion of the sensor current Is that is attributable to thebaseline capacitance of the capacitive sensor 521.

The analog multiplexer bus 530 connects components within integratedcircuit chip 500, and is also coupled to ground through a capacitance C₁531. In one embodiment, the bus 530 can be used to selectively connectcomponents within chip 500 to other components within the chip 500.

The current mirror 560 is external to integrated circuit chip 500 andconnects to the analog multiplexer bus 530 through output pin 503. Acompensated sensor current I_(D) 561, which represents the differencebetween the sensor current and the compensation current, flows into theoutput pin 503 from current mirror 530. Current mirror 530 generates amirror current I_(M) 566 based on the compensated sensor current I_(D)561. In one embodiment, the current mirror 560 generates a mirrorcurrent I_(M) 566 that is approximately equal to the compensated sensorcurrent I_(D) 561. In alternative embodiments, the mirror current I_(D)566 is proportional to the compensated sensor current I_(D) 561according to a predetermined ratio.

I_(M) 566 flows through R₃ 567 to ground such that the voltage across R₃567 can be expressed as V_(R3)=I_(M)×R₃. Thus, the GPIO port 520 that isconnected to R₃ 567 through input pin 504 can be used as a measurementcircuit to determine the capacitance of capacitive sensor 521 based onthe voltage V_(R3).

In one embodiment, the GPIO port 520 determines whether an input ispresent at capacitive sensor 521 based on whether V_(R3) exceeds athreshold voltage. For example, GPIO port 520 may assert a signal toindicate an input in response to detecting a value of V_(R3) thatexceeds a threshold voltage of 3 volts. In one embodiment, GPIO port 520is a high impedance input so that the current passing through R₃ 567 isapproximately equal to I_(M) 566.

FIG. 6 illustrates one embodiment of a capacitance measuring circuitimplemented in an integrated circuit chip. Integrated circuit chip 600includes a system clock connected to switches 622, 623, 672, and 673,analog multiplexer bus 630 with a capacitance 631 to ground, currentdigital-to-analog converter (IDAC) 641, and measurement circuit 680.Measurement circuit 680 includes a discharge switch 681, comparator 682,and counter 685.

A number of capacitive sensors including sensors 621 and 671 areconnected to the integrated circuit chip 600 through a set of input pinsincluding input pins 602 and 605. A current mirror 560 is connected tosupply voltage V_(CC) through resistors R₁ 662 and R₂ 663, and isconnected to the integrated circuit chip 600 through output pin 603. Thecurrent mirror 560 is also connected to the measurement circuit 680through input pin 604, and is coupled with ground through integrationcapacitor C_(INT) 657.

Capacitive sensors 621 and 671 are sensors in a set of capacitivesensors connected to the integrated circuit chip 600. In one embodiment,capacitive sensors 621 and 671 are individual capacitive sensors in anarray of sensors. For example, a touchpad or slider input device mayinclude a number of capacitive sensing elements, and each of thosesensing elements may correspond to a capacitive sensor such as sensor621 or 671. In one embodiment, the set of capacitive sensors include Nsensors, where capacitive sensor 621 represents the first sensor in theset, and sensor 671 represents the Nth sensor in the array. Each of thesensors in the set is connected to the integrated circuit chip 600through a set of input pins including input pins 602 and 605.

Each of the capacitive sensors in the set of sensors is connectedthrough an input pin to a set of switches, which is in turn connected tothe analog multiplexer bus 630. For example, capacitive sensor 621 isconnected through input pin 602 to switches 622 and 623. Similarly,sensor 671 is connected through input pin 605 to switches 672 and 673.Switches 622, 623, 672, and 673 are operated in a non-overlapping mannerto repeatedly charge and discharge the capacitive sensors 621 and 671.In one embodiment, the switches are controlled by a system clock 610.The operation of switches 622 and 623 results in a sensor current I_(S1)624 from the analog multiplexer bus 630 to ground. Similarly, theoperation of switches 672 and 673 results in a sensor current I_(SN) 476from the bus 630 to ground.

The analog multiplexer bus carries analog signals and may be used toselectively connect components within the integrated circuit chip 600with other components in the chip 600. In one embodiment, the bus 630 isused to selectively connect each one of the sensors in the set ofcapacitive sensors independently to the current mirror 560 andmeasurement circuit 680. This allows a single measurement circuit 680 tomeasure capacitances of each of the sensors individually.

For example, where the set of capacitive sensors is a sensor array in atouch slider device, the measurement circuit may measure thecapacitances of each of the capacitive sensor elements in the array todetermine the location of an input on the slider device. The array ofsensors is scanned using the analog multiplexer bus 630 to connect eachof the capacitive sensor elements to the measurement circuit 680 insequence. In alternative embodiments, the analog multiplexer bus 630 maysimultaneously connect more than one of the sensors in the set ofcapacitive sensors to the measurement circuit.

IDAC 641 is used as a compensation circuit, and may be programmed tosupply a compensation current to the analog multiplexer bus 630. In oneembodiment, the compensation current is approximately equal to a portionof the sensor current I_(S1) 624 or I_(SN) 674 attributable to thebaseline capacitances of the sensors 621 and 671, respectively. In oneembodiment where the baseline capacitances of the sensors 621 and 671are different, the IDAC 641 is programmed to supply a differentcompensation current for each sensor. For example, IDAC 641 may storedifferent compensation current levels in a memory and output anappropriate level to compensate the baseline capacitance of whichevercapacitive sensor is connected to the measurement circuit 680 throughanalog multiplexer bus 630.

The current mirror 560 is connected to analog multiplexer bus 630through output pin 603. Compensated sensor current I_(D) 651, whichrepresents the difference between the compensation current from IDAC 641and the sensor current (i.e., I_(S1) 624 or I_(SN) 674), flows from thecurrent mirror 560 to the bus 630. Current mirror 560 generates a mirrorcurrent I_(M) 656 that is proportional to I_(D) 651. In one embodiment,I_(M) 656 is equal to I_(D) 651. In alternative embodiments, I_(M) 656is proportional to I_(D) 651 according to a predetermined ratio. In suchcases, current mirror 560 may be used to increase or decrease themagnitude of I_(D) 651 to meet the input requirements of measurementcircuit 680.

The measurement circuit 680 measures the mirror current I_(M) 656generated by the current mirror 560 to determine the capacitance ofwhichever capacitive sensor is connected through bus 630. The mirrorcurrent I_(M) 656 charges an integration capacitor C_(INT) 657. C_(INT)657 is connected to an input of comparator 682 so that as the charge onC_(INT) 657 increases, the voltage at the comparator 682 inputincreases. When the voltage at the input of comparator 682 exceeds athreshold V_(REF) 683, the comparator 682 asserts its output. Thecomparator 682 output, when asserted, closes the discharge switch 681 todischarge the integration capacitor C_(INT) 657. As C_(INT) 657 isdischarged, the voltage at the comparator input drops below V_(REF) 683and the comparator 682 deasserts its output in response.

Thus, the comparator outputs a series of pulses as C_(INT) 657 isrepeatedly charged and discharged. The time between the pulses dependson the magnitude of I_(M) 656, which in turn depends on the capacitanceof whichever capacitive sensor is connected to the bus 630.

In one embodiment, the measurement circuit 680 includes a timer 686 thatperiodically discharges C_(INT) 657 by closing discharge switch 681.Timer 686 suppresses the output of comparator 682 if the rate of thevoltage increase at C_(INT) 657 does not exceed a threshold rate ofvoltage increase.

In one embodiment, counter 685 outputs a count value indicating theamount of time passing between pulses output by the comparator 682. Inan alternative embodiment, the count value indicates a number of pulsesoutput by the comparator 682 within a given time period. The count valuecan be transmitted to a computer system for further processing.

FIG. 7A is a graph illustrating the signals associated with theoperation of one embodiment of a capacitance sensing circuit, such asthe capacitance sensing circuit described with reference to FIG. 6. Thegraph of FIG. 7A illustrates signals of the capacitive sensing circuitwhen no input is present at the capacitive sensor being measured by thecapacitance sensing circuit.

The capacitive sensing circuit implemented by integrated circuit chip600 measures the capacitance of capacitive sensor 621 by connecting thesensor 621 with the current mirror 560 and the measurement circuit 680using analog multiplexer bus 630. In one embodiment, when no input ispresent at capacitive sensor 621, the compensation current supplied byIDAC 641 approximately cancels the sensor current I_(S1) 624 so that thecompensated sensor current I_(D) 651 is very small. Accordingly, themirror current I_(M) 656 that is generated by the current mirror basedon the magnitude of I_(D) 651 is correspondingly small.

When I_(D) is used to charge the integration capacitor C_(INT) 657, therate of the voltage increase across C_(INT) 657 is slow. In oneembodiment, the charging of C_(INT) 657 by mirror current I_(M) 656begins at measurement start point 732. At measurement start point 732,the integration capacitor voltage V_(INT) 730 across integrationcapacitor C_(INT) 657 increases over time, as C_(INT) 657 is charged,until C_(INT) 657 is discharged at discharge point 734. In oneembodiment, C_(INT) 657 is discharged at periodic intervals by timer686, as previously described with reference to FIG. 6. Since the chargerate of C_(INT) 657 is slow, V_(INT) 730 does not exceed the comparatorthreshold 720 before C_(INT) is discharged at point 734. The comparatorthreshold is set by the reference voltage V_(REF) 683 that is applied tothe comparator input.

Since V_(INT) 730 does not exceed comparator threshold 720, thecomparator 682 does not output any pulses, and the comparator output 710remains low, indicating that no input is present at the capacitivesensor 621. In one embodiment, the integration capacitor C_(INT) 657 isdischarged periodically even when the comparator threshold 720 is notexceeded.

FIG. 7B is a graph illustrating signals of the capacitive sensingcircuit when an input is present at the capacitive sensor being measuredby the capacitance sensing circuit, according to one embodiment.

When an input is present at the capacitive sensor 621, the capacitanceof the sensor 621 increases so that more charge is stored and dischargedto ground for each cycle of switches 622 and 623. Accordingly, thesensor current I_(S1) 624 increases, resulting in a correspondingincrease in the compensated sensor current I_(D) 651. I_(M) 656 isgenerated by the current mirror 560 based on the magnitude of I_(D) 651,so that I_(M) 656 reflects the increase in I_(D) 651.

When the integration capacitor C_(INT) 657 is charged using I_(M) 656,the rate of charging is higher than when no input is present at thesensor 621. Accordingly, in contrast with the graph in FIG. 7A, thegraph in FIG. 7B illustrates this higher rate of charging over manycycles of charging and discharging the integration capacitor C_(INT)657. Specifically, the rate of increase of the integration capacitorvoltage V_(INT) 770 shows an increase corresponding to the increase inthe magnitude of I_(M) 656.

When an input is present at the sensor 621, the rate of increase ofV_(INT) 770 is sufficiently high that V_(INT) 770 exceeds the comparatorthreshold 760 before being discharged. Each time at which V_(INT) 770exceeds the comparator threshold 760 corresponds to a comparator triggerpoint, such as comparator trigger 752, where the comparator asserts itsoutput. At each comparator trigger point, a voltage pulse is generatedat the comparator output 750. The discharge 774 occurs when thecomparator output 750 causes the discharge switch 681 to discharge theintegration capacitor C_(INT) 657.

A counter 685 can count the number of pulses detected within a timeframe or measure the time between pulses to determine a capacitance ofthe capacitive sensor 621.

FIG. 8 is a flow diagram illustrating a process for sensing capacitanceof a capacitive sensor, according to one embodiment. Capacitance sensingprocess 800 may be implemented, for example, by capacitance sensingcircuits 200 and 400 illustrated in FIGS. 2 and 4, respectively.

At block 802, a sensor current I_(S) is generated by operating aswitching circuit connected to the capacitive sensor. For example, inswitching circuit 220, switch 222 charges capacitive sensor 221 whileswitch 223 is open. Switch 222 opens and switch 223 closes to dischargethe sensor 221 to ground. In one embodiment, switches 222 and 223 areopened and closed at a frequency determined by an oscillator or a clocksignal, and operate in a non-overlapping manner, so that switches 222and 223 are not simultaneously closed at any point in the switchingcycle.

The switching cycle results in a sensor current I_(S) 224 flowing fromnode 225 to ground. The magnitude of sensor current I_(S) 224 depends onthe capacitance of sensor 221, which is affected by the proximity of aconductive object near the sensor 221.

At block 804, an IDAC in a compensation circuit is programmed togenerate a desired compensation current. In one embodiment, thecompensation current cancels a portion of the sensor currentattributable to the baseline capacitance of the capacitive sensor 221.For example, I_(C) 242 may be approximately equal to the portion ofI_(S) 224 that is attributable to the baseline capacitance so that I_(C)242 flowing into node 225 added to I_(S) 224 flowing out of the node 225results in a net current flow of zero out of node 225 when no input ispresent at the sensor 221.

In one embodiment, this current setting may be determined during acalibration process. For example, while sensor current I_(S) 224 isbeing generated, a compensation current I_(C) 242 is supplied to node225 and the current setting for IDAC 241 is adjusted until thecompensated sensor current I_(D) 261, which represents a differencebetween I_(S) 224 and I_(C) 242, is approximately zero.

At block 806, the compensation current is added to the sensor current togenerate a compensated sensor current I_(D). For example, once the IDAC241 is programmed to provide a specific level of compensation currentI_(C) 242, the IDAC supplies I_(C) 242 into node 225, from which sensorcurrent I_(S) 224 is being drawn. The difference between I_(C) 242 andI_(S) 224 is the compensated sensor current I_(D) 261.

When the capacitance of sensor 221 is increased by an input, I_(S) 224increases because more charge is stored and discharged to ground by thesensor 221. Since I_(C) remains constant, I_(D) 261 increasescorrespondingly with I_(S) 224.

At block 808, a current mirror is used to generate a mirror currentI_(M) that is proportional to the compensated sensor current I_(D). Forexample, in capacitance sensing circuit 200, the compensated sensorcurrent I_(D) 261 flows into node 225 from transistor 264. Currentmirror 260 generates a mirror current I_(M) 266 based on the compensatedsensor current I_(D) 261. In one embodiment, I_(M) 266 is approximatelyequal to I_(D) 261. Alternatively, I_(M) 266 may be greater or smallerin magnitude than I_(D) 261 according to a desired proportion. Forexample, this proportion may be chosen to meet input requirements ofmeasurement circuit 280.

At block 810, a measurement circuit measures the mirror current I_(M) todetermine the capacitance of the capacitive sensor. In one embodiment, ameasurement circuit can determine the capacitance based on a voltageresulting from passing the mirror current through an impedance. Forexample, with reference to FIG. 4, the sense voltage 482 is generatedfrom passing mirror current I_(M) 466 through resistor R₃ 467. In oneembodiment, such a sense voltage may be compared to a threshold voltageso that an input at the capacitive sensor causes the sense voltage toexceed the threshold voltage.

Alternatively, the measurement circuit can determine the capacitance byusing the mirror current to charge an integration capacitor, asdescribed with reference to FIG. 9, as follows.

FIG. 9 is a flow diagram illustrating a process for measuring thecapacitance of a capacitive sensor using a mirror current to charge anintegration capacitor, according to one embodiment. The operationsrepresented by capacitance measurement process 900 correspond to theoperations of block 810 of capacitance sensing process 800, which may beimplemented, for example, by measurement circuits 280, or 680.

At block 902, the integration capacitor is discharged. For example, inmeasurement circuit 280, the integration capacitor C_(INT) 282 isdischarged by closing the discharge switch 281. The discharge switch 281is closed in response to comparator 284 asserting its output. Similarly,discharge switch 681 of measurement circuit 680 discharges C_(INT) 657in response to an asserted output at comparator 682.

At block 904, the integration capacitor is charged using the mirrorcurrent. For example, in capacitance sensing circuit 200, the chargingof C_(INT) 282 is initiated by opening discharge switch 282 so thatmirror current I_(M) 266 charges C_(INT) 282. In measurement circuit680, switch 681 is similarly opened to so that C_(INT) 657 is charged byI_(M) 656.

At block 906, the measurement circuit determines whether the voltageV_(INT) on the integration capacitor C_(INT) exceeds the referencevoltage V_(REF). For example, in sensing circuit 200, the voltageV_(INT), across capacitor C_(INT) 282, and V_(REF) 283 are applied tothe inputs of comparator 284, which compares the voltages. If V_(INT)exceeds V_(REF) 283, the process 900 continues at block 908.

At block 908, the comparator asserts its output in response todetermining that V_(INT) exceeds V_(REF). In the above example, when thevoltage V_(INT) across the integration capacitor C_(INT) 282 exceedsV_(REF) 283, the comparator 284 asserts its output. The process 900continues at block 902, where the assertion of the comparator 284 outputcauses the discharge of the integration capacitor, as previouslydescribed. The discharge of the integration capacitor 282 causes theintegration capacitor voltage V_(INT) to drop below V_(REF) 283 so thatthe comparator 284 deasserts its output. The repeated assertion andsubsequent deassertion of the comparator output results in a sequence ofpulses.

In one embodiment, a characteristic of the sequence of pulses can bemeasured to determine the capacitance of the capacitive sensor. Forexample, the capacitance may be detected using timer 285 in measurementcircuit 280. Timer 285 counts a number of oscillations or clock pulsesbetween the pulses output by the comparator 284. In one embodiment, thenumber of oscillations or clock pulses counted in between comparatorpulses corresponds to the capacitance of the sensor.

Alternatively, the sensor capacitance can be determined using a counter,such as counter 685, which counts the number of pulses output by thecomparator 682 within a set time period. The number of pulses detectedby the counter increases with the capacitance of the capacitive sensor.

If, at block 906, the integration capacitor voltage V_(INT) does notexceed V_(REF), the process 900 continues at block 910. At block 910,the measurement circuit determines whether a discharge duration haslapsed. If the discharge duration has lapsed, the measurement circuitcontinues at block 902, where the integration capacitor is discharged inresponse to determining that the discharge duration has lapsed. Forexample, in measurement circuit 680, the timer 686 may be configured toperiodically discharge integration capacitor C_(INT) 657 to ground byclosing discharge switch 681. With reference to FIG. 7A, thiscorresponds to the voltage drop of the integration capacitor voltage 730at discharge point 734.

In alternative embodiments, the discharge is triggered based on somecriteria other than lapse of a time period. Alternatively, theintegration capacitor may be discharged only when the comparator outputis asserted, and is not independently triggered by the operationsrepresented by block 910.

If, at block 910, the discharge duration has not lapsed, the process 900continues at block 904, where the measurement circuit continues tocharge the integration capacitor from the mirror current.

The embodiments described herein include a capacitance sensing circuitthat determines the capacitance of a capacitive sensor based on a mirrorcurrent generated by a current mirror, where the mirror current isgenerated based on a compensated sensor current. The inclusion of thecurrent mirror in such a capacitance sensing circuit, such ascapacitance sensing circuit 200, maintains a lower input impedance toincrease noise immunity, particularly at low frequencies.

The embodiments described herein may have the advantage of keeping allbenefits of switching capacitor methods (especially in the high immunityfor RF/EMI noise signals), and may be configured for easy implementationin existing devices from hardware and software perspectives, as well asin future devices.

Embodiments of the present invention, described herein, include variousoperations. These operations may be performed by hardware components,software, firmware, or a combination thereof. As used herein, the term“coupled to” may mean coupled directly or indirectly through one or moreintervening components. Any of the signals provided over various busesdescribed herein may be time multiplexed with other signals and providedover one or more common buses. Additionally, the interconnection betweencircuit components or blocks may be shown as buses or as single signallines. Each of the buses may alternatively be one or more single signallines and each of the single signal lines may alternatively be buses.

Certain embodiments may be implemented as a computer program productthat may include instructions stored on a machine-readable medium. Theseinstructions may be used to program a general-purpose or special-purposeprocessor to perform the described operations. A machine-readable mediumincludes any mechanism for storing or transmitting information in a form(e.g., software, processing application) readable by a machine (e.g., acomputer). The machine-readable medium may include, but is not limitedto, magnetic storage medium (e.g., floppy diskette); optical storagemedium (e.g., CD-ROM); magneto-optical storage medium; read-only memory(ROM); random-access memory (RAM); erasable programmable memory (e.g.,EPROM and EEPROM); flash memory; or another type of medium suitable forstoring electronic instructions.

Additionally, some embodiments may be practiced in distributed computingenvironments where the machine-readable medium is stored on and/orexecuted by more than one computer system. In addition, the informationtransferred between computer systems may either be pulled or pushedacross the communication medium connecting the computer systems.

Although the operations of the method(s) herein are shown and describedin a particular order, the order of the operations of each method may bealtered so that certain operations may be performed in an inverse orderor so that certain operation may be performed, at least in part,concurrently with other operations. In another embodiment, instructionsor sub-operations of distinct operations may be in an intermittentand/or alternating manner.

In the foregoing specification, the invention has been described withreference to specific exemplary embodiments thereof. It will, however,be evident that various modifications and changes may be made theretowithout departing from the broader spirit and scope of the invention asset forth in the appended claims. The specification and drawings are,accordingly, to be regarded in an illustrative sense rather than arestrictive sense.

What is claimed is:
 1. An integrated circuit (IC) comprising: a terminalconfigured to be coupled to a capacitive sensor element; a switchingcircuit coupled between the terminal and a compensation circuit; acurrent mirror having an input coupled to the switching circuit and thecompensation circuit, and an output coupled to a first input of acomparator; and wherein the switching circuit is configured to couplethe terminal to a first supply voltage in a first state and to thecompensation circuit and the current mirror in a second state.
 2. The ICof claim 1, wherein the compensation circuit is coupled between theswitching circuit and a second power supply voltage.
 3. The IC of claim1, wherein the first supply voltage is a ground voltage.
 4. The IC ofclaim 2, wherein the second supply voltage is a positive voltage.
 5. TheIC of claim 2, wherein the first supply voltage is a positive voltageand the second supply voltage is a ground voltage.
 6. The IC of claim 1,further comprising a timer circuit coupled to the output of thecomparator and clocked by an oscillator.
 7. The IC of claim 1, whereinthe capacitance of the capacitive sensor element is affected by theproximity of a conductive object.
 8. The IC of claim 1, furthercomprising a processing core coupled to the comparator and acommunication block coupled to the processing core, wherein thecommunication block is configured to communicate with a host processor.9. The IC of claim 1, wherein the compensation circuit comprises acurrent digital-to-analog-converter.
 10. A method comprising: providinga terminal configured to be coupled to a capacitive sensor element;providing a compensation circuit; providing a switching circuit coupledbetween the terminal and the compensation circuit; providing a currentmirror having an input coupled to the switching circuit and to thecompensation circuit; providing a comparator having a first inputcoupled to the output of the current mirror; configuring the terminal tobe coupled to a first supply voltage using the switching circuit in afirst state; and configuring the terminal to be coupled to thecompensation circuit and current mirror using the switching circuit in asecond state.
 11. The method of claim 10, further comprising configuringthe compensation circuit to be coupled to a second power supply voltage.12. The method of claim 10, wherein the first supply voltage is a groundvoltage,
 13. The method of claim 11, wherein the second supply voltageis a positive voltage.
 14. The method of claim 11, wherein the firstsupply voltage is a positive voltage and the second supply voltage is aground voltage.
 15. The method of claim 10, wherein the capacitance ofthe capacitive sensor element is affected by the proximity of aconductive object.
 16. The method of claim 10, further comprising:providing a processing core coupled to the comparator; providing acommunication block coupled to the processing core; and configuring thecommunication block to communicate with a host processor.
 17. A systemcomprising: a capacitive sensor element; a switching circuit coupledbetween the capacitive sensor element and a compensation circuit; acurrent mirror having an input coupled to the switching circuit and thecompensation circuit, and an output coupled to a first input of acomparator; a processing core coupled to an output of the comparator; acommunication block coupled to the processing core; and a host processorcoupled to the communication block, wherein the switching circuit isconfigured to couple the input terminal to a first supply voltage in afirst state and to the compensation circuit and current mirror in asecond state, and wherein the compensation circuit is coupled betweenthe switching circuit and a second power supply voltage.
 18. The systemof claim 17, wherein the first supply voltage is a ground voltage andthe second supply voltage is a positive voltage.
 19. The system of claim17, wherein the second supply voltage is a ground voltage and the firstsupply voltage is a positive voltage.
 20. The system of claim 17,wherein the compensation circuit comprises a currentdigital-to-analog-converter.